Integrated circuits are typically manufactured by forming and/or altering multiple layers on a semiconductor wafer. Particular steps may include depositing a layer, forming a pattern over the layer, and etching the pattern. Such steps may form various structures, including but not limited to trenches in a substrate, a transistor gate layer from a layer of polycrystalline silicon (polysilicon), contacts to a substrate/gate, various interconnect layers, and vias between interconnect layers.
One common method of forming patterns on a layer includes photolithography in conjunction with a photoresist layer. More particularly, a layer of photoresist may be deposited over a layer and patterned formed in the layer by shining light through a pattern.
Many current manufacturing processes photolithography steps are accomplished with a machine called a “stepper.” A stepper typically includes a light source and a reticle. A reticle can be designed to include (or ultimately) a desired pattern in an underlying layer of photoresist. A reticle may include the pattern for one die, or multiple dies.
In operation, a layer of photoresist can be deposited (e.g., spun) on the surface of a layer. A stepper may then “step” across the entire wafer, essentially developing the reticle pattern in the underlying photoresist layer. Undeveloped portions of a pattern may then be removed by a solvent, or the like.
It follows that the proper manufacturing of a semiconductor device can rely on assuming that the pattern contained in a reticle is good (i.e., ultimately produces a desired pattern in an underlying layer). Unfortunately, this is not always the case.
Various factors can contribute to a defect in a reticle. As but a few of the many possible examples, such defects may arise when a reticle is manufactured (a particle, unwanted spot, etc.), or may be inherent in a database that produces a reticle pattern (corrupted database, etc.).
Thus, prior to utilizing a new reticle in a manufacturing process, it is desirable to first inspect a reticle to ensure its pattern is valid.
Various factors can contribute to the importance of “proving” a reticle (ensuring its pattern is valid). A semiconductor device manufacturer often contracts a vendor to make a reticle. Therefore, in many cases, a manufacturer will not know if a reticle is good until it is received and inspected. Second, because reticle manufacturing is outsourced, if a reticle has a defect, there may be some turnaround time before a new reticle can be generated correcting any defects (of course the new reticle will also have to be inspected).
Various conventional methods for reticle inspection are known. As but one example, a reticle may inspected with a database-to-reticle inspection. Alternatively, a chip-to-chip comparison can be performed. A database-to-reticle inspection can prove the integrity of the photomask data, while the chip-to-chip comparison may be useful in detecting random defects or defocusing issues associated with the reticle fabrication. Such inspections may be performed in an automated fashion with inspection machines such as a KLA351 manufacture by KLA-Tencor Corporation, or an Orbit RT-8000 manufactured by Orbotech, Ltd., or the like.
Due to the very small feature sizes, and very large patterns of an integrated circuit layer, it is desirable to utilize an inspection machine to prove a reticle. Such inspection machines typically require a minimum contrast between edges of a pattern and open (i.e., non-patterned) areas.
A conventional method of inspecting a reticle with a patterned wafer will now be described with reference to FIGS. 3A-3E. FIGS. 3A-3E shows various steps in boxes on the right, with example illustrations of a method on the left.
Referring to FIG. 3A, a wafer can be prepared for a resist verification flow. In FIG. 3B, a layer of photoresist 304 can be formed on the wafer 302, by spinning, or the like. Processing can continue as shown in FIG. 3C with a reticle 308 selectively exposing portions of a resist covered wafer to a light source, or the like. A FIG. 3D shows photoresist pattern 310 which may be formed after a photoresist layer has been developed, and undeveloped portions have been removed. In this way, a pattern in a reticle can be transferred to a layer of photoresist.
Finally, a wafer can be inspected in FIG. 3E for pattern defects and anomalies.
A method according to FIGS. 3A-3E may have several drawbacks. Because a pattern may be formed directly on a wafer, there can be little contrast between the exposed and unexposed areas of the wafer. This can make inspection difficult. In addition, the various exposure parameters used to form a layer in photoresist may be different from those used to form an actual semiconductor device. In particular, in production (the manufacturing of a device), a patterned layer may be higher from the surface, resulting a patterned being developed in a different focal plane. Still further, the amount of light (or other developing form of radiation) may differ between an inspection pattern, and that used in production. Consequently, conventional inspection processes that transfer a pattern into a photoresist may not adequately reproduce a pattern or provide sufficient contrast in a pattern.
A finished conventional inspection wafer may have further drawbacks. A pattern of photoresist formed on a wafer surface may not provide sufficient contrast to enable an inspection machine to automatically align a wafer. This can be time consuming and add a manually intensive task to an inspection method.
Yet another drawback to a conventional inspection process, such as that shown in FIGS. 3A to 3E, can be the difficulty in examining various features at a high magnification. More particularly, many features may have to be examined under a scanning electron microscope (SEM). Unfortunately, photoresist may have a tendency to charge under an electron beam. While low energy electron beam systems may be capable of reducing charging, such systems can be expensive and do not always completely eliminate charging. Charging can lead to periodic flashes, and/or bright spots that may obstruct or distort a feature under examination, thereby preventing accurate verification of a feature and or measurement of a defect.
Another conventional method, as noted above, can be an inspection following a short-loop flow. A short-loop flow is so named because a wafer is taken through only a portion of the chip processing flow. While this may add complexity to a flow such as that shown in FIGS. 3A-3E, it can also use recipes, equipment, and/or lithography step of an existing process. Thus, exposure and focus settings of a short loop inspection wafer can be essentially the same as a production wafer. This is in contrast to the example of FIGS. 3A to 3E, where a photoresist may be underexposed or developed in a different focal plane.
Short-loop flows may also have drawbacks, however. A short-loop flow adds more complexity to a process. Still further, each additional process step in a short loop may introduce defects not associated with, or resulting from, a reticle defect. As but one example, chemical-mechanical-polishing (CMP) may increase the number of particles on wafer. This can distract the inspection system from detecting true reticle related defects.
In light of the above, it would be desirable to arrive at some way of verifying reticles that does not suffer from the various drawbacks of conventional approaches, such as those noted above.